12G CoaXPress v2.0 FPGA IP Core: Host (Frame Grabber)
Features
Applications:
- High speed cameras
- High definition cameras
- Frame Grabbers
- Panoramic cameras
- Upgrade for legacy coax based systems
- Defense remote systems
- Automotive surround view system
- Surveillance
- Robotic Vision
The CoaXPress v2.0 IP Core from KAYA Instruments supports GenICam international standards, providing a generic programming interface for all kinds of cameras regardless of the interface technology. The CoaXPress v2.0 IP Core from KAYA Instruments provides a Multi-link high-performance solution for rate-demanding video applications. Both Host and Device modes of operation are supported. The IP core offers support for the newest and industry-leading Artix, Kintex, Virtex, and Zynq FPGAs, including all 7, Ultrascale and Ultrascale+ families from Xilinx, Cyclone V, Cyclone 10, Arria V GX, Arria V GZ, Arria 10, Stratix IV, Stratix V, and Stratix 10 FPGAs from Intel (former Altera) and PolarFire from Microsemi. The host IP core incorporates a friendly streaming interface with a highly configurable pixel packer for glueless connection to imaging sensors or user logic.
Specifications
- Compliant with JIIA NIF-001-2019 CoaXPress standard rev 2.0
- CXP v2.0 support of up to 12.5 Gbps high speed link and up to 41 Mbps low speed link
- Multiple link rates support
- Supports both Host and Device modes
- Multiple CoaXPress v2.0 links suited for applications demanding high throughput.
- Multiple video stream support
- Build in FPGA SerDes, no need for additional design effort
- AXI4L/Avalon MM support for control channel
- Highly configurable pixel packer
- Host IP Core supports multiple device connection on different data rates
- Embedded CRC-32 generate/check for streaming data packets
- Avalon and AXI4 Stream Interface Profile in Host IP Core
- Dedicated ports to for GPIO and trigger
Core Details
- Single or multi-use license
- Free license for KAYA Instruments CoaXPress Mezzanine card users
- Soft IP core: RTL-encrypted source code, synthesis scripts, etc.
- Comprehensive documentation package
- Support for Altera®, Xilinx® and PolarFire from MicroSemi FPGAs
- Language: Verilog HDL
- Simulation environment: ModelSim
Supported Devices
| FPGA Device Family | P.N. | CoaXPress Host (Rx) | Example Design |
| Artix7 | XC7A***T | V | Artix7 evaluation board – AC701 |
| Kintex7 | XC7K***T | V | Kintex7 evaluation board – KC705 |
| Kintex7 ultrascale | XCKU*** | V | Kintex7 ultrascale evaluation board – KCU105 |
| Kintex7 ultrascale+ | XCKU*** | V | Kintex7 ultrascale+ evaluation board – KCU116 |
| Virtex7 ultrascale+ | XCVU*** | V | Virtex7 ultrascale+ evaluation board – VCU118 |
| Virtex7 with GTX transceiver | XC7VX***T | V | Virtex7 evaluation board – VC707 |
| Virtex7 with GTH transceiver | XC7VX***T | V | Virtex7 evaluation board – VC709 |
| Zync 7000 (1) | XC7Z*** | V | Zynq-7000 evaluation board – ZC702 |
| Zync ultrascale+ | XCZU*** | V | Zynq ultrascale+ evaluation board – ZCU102 |
| Cyclone V GX | 5CGXF***6*** | V | Cyclone V GX FPGA development board |
| Cyclone V SX | 5CSXF*** | on demand | Cyclone V SX FPGA development board |
| Cyclone 10 | 10CX*** | V | Cyclone 10 FPGA development board |
| Stratix V GX | 5SGX*** | V | Stratix V GX FPGA development board |
| Stratix IV GX | EP4SGX****** | on demand | Stratix IV GX FPGA development board |
| Stratix 10 GX | 1SGX****** | V | Stratix 10 GX FPGA development board |
| Arria V GZ | 5AGZ*** | V | KOMODO CoaXPress |
| Arria V GX | 5AGX****4*** | V | Arria V GX FPGA development board |
| Arria V SX | 5ASX****4*** | on demand | Arria V SX FPGA development board |
| Arria 10 SX | RXCA****4*** | V | Arria 10 SX FPGA development board |
| Arria 10 GX | 10AX*** | V | Arria 10 GX FPGA development board |
| Versal AI Core | VC*** | on demand | Versal AI Core series evaluation board – VCK190 |
| Versal Prime | VM*** | on demand | Versal Prime series evaluation board – VMK180 |
(1) Only for devices that have GTP or GTX transceivers available.
