FPGA CoaXPress IP Core – Host

Build FPGA frame grabbers and image-acquisition systems with KAYA Instruments’ CoaXPress Host IP Core, supporting CoaXPress over coaxial cable and CoaXPress over Fiber (CoF) with the KAYA Multi-Link Host CoF Bridge.

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Applications

KAYA Instruments’ CoaXPress Host IP Core provides a multi-link receiver solution for high-bandwidth image acquisition. It supports CoaXPress v2.0, with backward compatibility to v1.1, and GenICam-compliant image formats for area-scan, line-scan, multi-ROI and multi-stream applications.

The host IP receives image data from connected cameras and provides a configurable DMA video streaming interface with an internal pixel unpacker for connection to downstream processing or user logic. It supports up to eight video streams and video output widths up to 256 bits per clock per stream.

Coaxial implementations support high-speed link rates up to 12.5 Gbit/s and low-speed control up to 41.6 Mbit/s, depending on the FPGA and configuration. Up to four CoaXPress links are supported as standard, with additional links available on request.

CoaXPress over Fiber support

For optical connectivity, combine the Host IP Core with KAYA Instruments’ Multi-Link Host CoaXPress over Fiber Bridge. The bridge connects the CoaXPress host interface to a compatible 10G Ethernet physical layer through XGMII, enabling fiber-based camera-to-frame-grabber connections.

  • Support for one to four parallel fiber links.
  • A 10 Gbit/s interface per link with an effective bit rate equivalent to CXP-12 without the coaxial link’s 8b/10b encoding overhead.
  • High-speed image-data reception from the device and low-speed control transmission from the host.
  • Implementation based on the CoaXPress over Fiber Bridge Protocol v1.0 (JIIA CXPR-008-2021); integration requirements and protocol exceptions are documented in the Host CoF Bridge manual.

The Host documentation includes the CoaXPress IP datasheet and core manual, the dedicated Host CoF Bridge manual, and a Host CoF reference-design guide for AMD/Xilinx FPGAs covering Vivado hardware configuration and Vitis software setup. Select the FPGA, physical layer and optical components for the required link configuration.

Easy to use

As a leader in the industry, KAYA instruments has been providing IP to hundreds of clients since 2008.  The IP provided is fully developed and supported by a team of industry veterans.  We provide multiple versions of the IP for the requirements you need.  Our IP is licensed to the client and not per seat.  Our affordable option(s) provide a customizable solution to best suit your needs.

Availability

Encrypted Netlist:
Try our fully functional IP to evaluate its advanced features, ease of use, and comprehensive documentation. When executed, our IP will run for a 30-minute test period.

Included with FMC Boards (Encrypted Netlist):
Develop your application with a copy of our IP on a single PC, included with your FMC board purchase. This allows for easy integration with your FPGA without the need to purchase the full IP.

Netlist IP:
Develop your complete system with our Encrypted Netlist IP. Utilize our IP on one of the compatible FPGAs listed in the compatibility section to develop your application. This package includes up to 10 hours of professional support and is licensed for use on a single PC or server.

Source Code:
Develop a complete system with our full, untethered IP. Modify and edit our code to utilize it in any environment or FPGA. This option includes up to 24 hours of technical support.

For CoaXPress over Fiber projects, contact KAYA Instruments to select the Host IP and Host CoF Bridge configuration and confirm the applicable licensing and evaluation package.

Supported Devices

The following Host IP configurations are listed in the March 2025 Host IP datasheet. Link rates refer to CoaXPress over coaxial cable. CoaXPress over Fiber additionally requires a supported Host CoF Bridge configuration and a compatible physical layer.

AMD (Xilinx)

FPGA device family CoaXPress Host (Rx) Maximum coax link rate Reference design board
Artix 7 Supported 6.25 Gbit/s AC701
Artix UltraScale+ Supported 12.5 Gbit/s On request
Kintex 7 Supported 12.5 Gbit/s KC705
Kintex UltraScale Supported 12.5 Gbit/s KCU105
Kintex UltraScale+ Supported 12.5 Gbit/s KCU116
Zynq-7000 Supported 12.5 Gbit/s ZC706
Zynq UltraScale+ Supported 12.5 Gbit/s ZCU102 / ZCU111
Virtex 7 Supported 12.5 Gbit/s VC709
Virtex UltraScale Supported 12.5 Gbit/s VCU108
Virtex UltraScale+ Supported 12.5 Gbit/s VCU118
Versal AI Core On request 12.5 Gbit/s On request
Versal Prime On request 12.5 Gbit/s On request

Altera

FPGA device family CoaXPress Host (Rx) Maximum coax link rate Reference design board
Cyclone V GX On request 6.25 Gbit/s DK-DEV-5CGXC7NES
Cyclone V SX On request 6.25 Gbit/s On request
Cyclone 10 Supported 12.5 Gbit/s DK-DEV-10CX220-A
Stratix V GX On request 12.5 Gbit/s DK-DEV-5SGXEA7N
Stratix 10 GX Supported 12.5 Gbit/s On request
Arria V GZ On request 6.25 Gbit/s On request
Arria V GX On request 6.25 Gbit/s DK-START-5AGXB3N
Arria V SX On request 6.25 Gbit/s On request
Arria 10 SX Supported 12.5 Gbit/s DK-START-10AS066
Arria 10 GX Supported 12.5 Gbit/s DK-DEV-10AX115

Microchip (Microsemi)

FPGA device family CoaXPress Host (Rx) Maximum coax link rate Reference design board
PolarFire MPF100T Supported 12.5 Gbit/s DVP-102-000521-001
PolarFire MPF200T Supported 12.5 Gbit/s On request
PolarFire MPF300T Supported 12.5 Gbit/s DVP-102-000481-001

AMD and Altera configurations are listed with encrypted-netlist and source-code options; PolarFire configurations are listed with source code. Additional FPGA devices, evaluation-board reference designs and custom hardware support are available on request.

CoaXPress over Fiber FPGA configurations

The Host CoF Bridge manual lists Zynq-7000, Zynq UltraScale+, Kintex UltraScale and UltraScale+, Virtex UltraScale and UltraScale+, Artix UltraScale+, Cyclone 10, Stratix 10, Arria 10, and PolarFire MPF100 / MPF200 / MPF300 targets. The documentation also includes a Host CoF reference-design guide for AMD/Xilinx FPGAs. Contact KAYA Instruments to confirm the Host IP, CoF Bridge, transceiver and reference-design configuration for your selected FPGA.

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